High-speed visualisation of your FPGA wires

By Anders Pedersen Sekanina · August 2025 · ← Back to blog

In August 2025 I gave the talk "High-Speed Visualization of Any of Your FPGA Wires" at GLA Summit – the LabVIEW community's international online conference. Here is a brief overview of the problem and the solution. The full recording can be watched at the bottom of this post.

The problem: FPGA debugging is slow or bandwidth-heavy

When developing LabVIEW FPGA applications on, for example, a CompactRIO, you often want to see and log what is happening on the internal signals – both during development and when the system is running in the field. The classic methods each have their cost: reading signals via the front panel is slow (around 500 samples per second) and takes up space on the FPGA. Using a DMA FIFO you can reach 200,000 samples per second – but if you are monitoring 50 signals, that quickly adds up to more than 12 Mbit/s that needs to be moved and stored.

The case: 50+ signals on 10–15 CompactRIOs

The starting point was a customer project with over 50 mixed analogue and digital signals per CompactRIO – distributed across 10–15 units. The customer wanted to be able to log all signals but only needed to view some of them at any given time.

The solution: dynamic signal selection with optimal bandwidth

FPGAs are not good at dynamic behaviour – the logic is fixed once compiled. The trick is therefore to keep the FPGA logic simple and let the host side control which signals are selected. The selected signals are packed into 1–5 64-bit words per sample: the first word contains for example 24 bits of timing and 19 digital signals, and the following words are packed with analogue channels. This way you only use the bandwidth that corresponds to the signals you are actually looking at – while still being able to reach any signal in the system.

Watch the talk and get the code

The full talk – including a demo and a takeaway on automatic FPGA compilation – can be watched here:

If the video does not play here, it can be watched directly on YouTube.

The code from the talk is open source and can be downloaded from GitLab.

If you have your own challenges with FPGA, Real-Time or data logging in LabVIEW, please get in touch.

/Anders Pedersen Sekanina